The present invention relates to testing of complex logic circuits and, more particularly, to reconfigurable register bit-slices for use in built-in logic block observers (i.e. BILBOs).
Traditionally, large scale integrated circuits have needed to be tested for defects or flaws. When only a fraction of the total components produced by a manufacturing process are "good" (i.e., meet the requirements of specifications), something must separate the "good" components from components which contain defects or flaws. Testing does this by applying input stimulus (input test patterns) to the device-under-test and comparing the outputs of the device-under-test with the expected "good" results.
In the past, test pattern generation has been done by hand or with a limited amount of aid from a computer. As the designs of the circuits being tested become increasingly complex, the test time required to generate test patterns by hand increases significantly.
An alternative to expensive manual test pattern generation exists. Designers can incorporate a number of simple design techniques into their circuit design which will reduce the cost of test pattern generation and application while actually allowing better test quality. In addition, it is possible to build into the circuit to be tested a number of capabilities typically required of external test equipment. These built-in self-test (BIST) techniques can greatly simplify automatic test equipment requirements and can result in significant costs savings.
Although testability-improvement techniques and built-in self-test techniques are attractive from the perspective of test cost reduction, they carry with them some significant costs which must be evaluated. Most design-for-test techniques consume chip real estate, power, I/O pins and may impact the speed performance of the circuit during normal operation.
Designs which use built-in self-test provide for generation of input stimulus and evaluation of the circuit response within the actual circuit design. To minimize the on-chip circuitry, external sequencing of the self-test operation is often used. A variety of methods exist for both providing the input stimulus and evaluating the circuit response. One such method is built-in self-test with pseudo-random test patterns.
The addition of a test pattern generator, a parallel signature analysis register, and a serial-scan register to a logic circuit for testing purposes consumes chip real estate and power. A solution to the problem of adding a plurality of test components to a logic circuit exists which combines the needed functions into a single register. This register is known as a built-in logic block observer (i.e. BILBO).
In order to support the various modes of operation, each BILBO register bit-slice requires front-end logic which reconfigures the register to a synchronized set, a serial-scan a test pattern generator, a signature analysis or a normal (i.e. parallel load) operational mode. Control inputs of the front-end logic are used to determine the operational mode of the BILBO.
BILBO registers can be strategically placed throughout a logic circuit to provide means for testing sections of the logic circuit. In a typical scenario, a first BILBO register is configured as a test pattern generator and a second BILBO register is configured as a signature analysis register. The test pattern generator applies a sequence of patterns to a section of a logic circuit while the results of the pattern sequence are compacted by the signature analysis register. When the test pattern sequence is complete, the second BILBO register is reconfigured as a serial-scan register and the compacted results are transferred to another location.
Current designs of BILBO registers comprise a plurality of bit-slices logically coupled together. The bit-slices comprise front-end logic which must switch more than one current switch along a signal path from a data input to an input of a memory device (e.g. bi-stable multi-vibrator) while operating in normal mode (i.e. parallel load). This switching causes a register in normal operational mode to perform at a slower rate than real-time speed. Real-time speed, in this instance, is considered the rate at which a register without front-end logic operates during the normal operational mode. It is desirable to utilize front-end logic which has minimal speed impact upon normal register operation.
The present invention overcomes the problem of real-time speed operation during normal operation inherent in previous BILBO register designs. Through clever logic design techniques, the present invention provides front-end logic for a BILBO register bit-slice which switches one current switch along a signal path from a data input to an input of a memory device (e.g. bi-stable multi-vibrator). The delay caused by the switching of a one current switch is equivalent to the delay associated with a 2:1 multiplexer or approximately one gate of delay. Thus, near real-time speed is obtained during the normal operational mode because a single current switch occurs along the signal path.